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authorAlan Cox <alc@FreeBSD.org>2025-06-28 19:49:26 +0000
committerAlan Cox <alc@FreeBSD.org>2025-07-03 21:30:02 +0000
commit1c1acaf6858be301384fd20b402cf2df831507a7 (patch)
tree9a2594bb95ea16cb3c1e2e7acdca7de55eb95187
parent906d7a4b521c19b2b1ae3ec844b5d4626f2fd529 (diff)
amd64: enable EFER.TCEHEADmain
Setting this option tells AMD processors that targeted TLB invalidation instructions, such as invlpg, only have to invalidate cached entries from the upper levels of the page table that lie along the path to the targeted virtual address. Otherwise, by default, all cached entries from the upper levels of the page table are invalidated. After unmapping a page table page we always perform a TLB invalidation that will invalidate any cached references to that page table page, so this option is safe to enable. Reviewed by: kib, markj Tested by: dougm Differential Revision: https://reviews.freebsd.org/D51093
-rw-r--r--sys/amd64/amd64/initcpu.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c
index 05e482f7783b..7f317674907e 100644
--- a/sys/amd64/amd64/initcpu.c
+++ b/sys/amd64/amd64/initcpu.c
@@ -325,6 +325,10 @@ initializecpu(void)
wrmsr(MSR_EFER, msr);
pg_nx = PG_NX;
}
+ if ((amd_feature2 & AMDID2_TCE) != 0) {
+ msr = rdmsr(MSR_EFER) | EFER_TCE;
+ wrmsr(MSR_EFER, msr);
+ }
hw_ibrs_recalculate(false);
hw_ssb_recalculate(false);
amd64_syscall_ret_flush_l1d_recalc();